Invention Grant
US07657851B2 Device, system, and method for correction of integrated circuit design
失效
用于校正集成电路设计的装置,系统和方法
- Patent Title: Device, system, and method for correction of integrated circuit design
- Patent Title (中): 用于校正集成电路设计的装置,系统和方法
-
Application No.: US11771152Application Date: 2007-06-29
-
Publication No.: US07657851B2Publication Date: 2010-02-02
- Inventor: Ilya Granovsky , Boaz Yeger
- Applicant: Ilya Granovsky , Boaz Yeger
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Suzanne Erez
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Device, system and method of correcting an integrated circuit design. For example, a method includes receiving a list of one or more root points for an active netlist that requires logic correction, wherein the root points correlate between elements of the active netlist and elements of a re-synthesized netlist that is based on a high-level correction for the integrated circuit design; automatically identifying in the active netlist a driving logic cone for at least one of the root points; and automatically identifying in the re-synthesized netlist a driving logic cone for the respectively correlated root point, including one or more corrected logic elements that correspond to the one or more identified flawed logic elements.
Public/Granted literature
- US20090007034A1 Device, System, and Method for Correction of Integrated Circuit Design Public/Granted day:2009-01-01
Information query