Invention Grant
US07657891B2 Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
有权
具有优化线程调度器的多线程微处理器,可提高管道利用效率
- Patent Title: Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
- Patent Title (中): 具有优化线程调度器的多线程微处理器,可提高管道利用效率
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Application No.: US11051979Application Date: 2005-02-04
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Publication No.: US07657891B2Publication Date: 2010-02-02
- Inventor: Michael Gottlieb Jensen , Darren M. Jones , Ryan C. Kinter , Sanjay Vishin
- Applicant: Michael Gottlieb Jensen , Darren M. Jones , Ryan C. Kinter , Sanjay Vishin
- Applicant Address: US CA Sunnyvale
- Assignee: MIPS Technologies, Inc.
- Current Assignee: MIPS Technologies, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/40

Abstract:
A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.
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