Invention Grant
- Patent Title: Localized biasing for silicon on insulator structures
- Patent Title (中): 硅绝缘体结构的局部偏置
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Application No.: US10930001Application Date: 2004-08-30
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Publication No.: US07659152B2Publication Date: 2010-02-09
- Inventor: Fernando Gonzalez , John K. Zahurak
- Applicant: Fernando Gonzalez , John K. Zahurak
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L21/84
- IPC: H01L21/84

Abstract:
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
Public/Granted literature
- US20050032284A1 Localized biasing for silicon on insulator structures Public/Granted day:2005-02-10
Information query
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