Invention Grant
US07659158B2 Atomic layer deposition processes for non-volatile memory devices
失效
用于非易失性存储器件的原子层沉积工艺
- Patent Title: Atomic layer deposition processes for non-volatile memory devices
- Patent Title (中): 用于非易失性存储器件的原子层沉积工艺
-
Application No.: US12059782Application Date: 2008-03-31
-
Publication No.: US07659158B2Publication Date: 2010-02-09
- Inventor: Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
- Applicant: Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/788
Abstract:
Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.
Public/Granted literature
- US20090242957A1 ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES Public/Granted day:2009-10-01
Information query
IPC分类:
