Invention Grant
- Patent Title: Manufacturing method of high voltage semiconductor device that includes forming a nitride layer on shallow trench isolations
- Patent Title (中): 包括在浅沟槽隔离层上形成氮化物层的高电压半导体器件的制造方法
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Application No.: US11905806Application Date: 2007-10-04
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Publication No.: US07659177B2Publication Date: 2010-02-09
- Inventor: Yong Keon Choi
- Applicant: Yong Keon Choi
- Applicant Address: KR Seoul
- Assignee: Dongku Hitek Co., Ltd.
- Current Assignee: Dongku Hitek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: KR10-2006-0104778 20061027
- Main IPC: H01L21/762
- IPC: H01L21/762

Abstract:
Disclosed is a semiconductor device, and more particularly, a manufacturing method of a high voltage semiconductor device. The method includes: forming a semiconductor substrate having a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage device; forming an oxide film on the substrate; and forming an insulating film on the oxide film. After removing the insulating film, the method includes forming a plurality of shallow trench isolations (STI's) in the areas of the substrate; forming a nitride layer on the substrate and on STIs; sequentially forming a plurality of wells and drift areas by implanting an impurity ion into the high voltage area; and sequentially forming the plurality of wells and the drift areas by implanting an impurity ion into the low voltage area. A system on chip (SOC) process may thus be simplified.
Public/Granted literature
- US20080102600A1 Manufacturing method of high voltage semiconductor device Public/Granted day:2008-05-01
Information query
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