Invention Grant
- Patent Title: In-situ deposition for Cu hillock suppression
- Patent Title (中): Cu小丘抑制的原位沉积
-
Application No.: US12186936Application Date: 2008-08-06
-
Publication No.: US07659198B2Publication Date: 2010-02-09
- Inventor: Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
- Applicant: Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
Public/Granted literature
- US20090035937A1 In-Situ Deposition for Cu Hillock Suppression Public/Granted day:2009-02-05
Information query
IPC分类:
