Invention Grant
- Patent Title: Process for manufacturing semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件制造工艺
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Application No.: US12127564Application Date: 2008-05-27
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Publication No.: US07659201B2Publication Date: 2010-02-09
- Inventor: Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
- Applicant: Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP10-209857 19980724
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
Public/Granted literature
- US20080233736A1 PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2008-09-25
Information query
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