Invention Grant
US07659213B2 Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same
有权
具有嵌入式拉伸应变层的晶体管,其具有减小的偏移到栅电极的方法及其形成方法
- Patent Title: Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same
- Patent Title (中): 具有嵌入式拉伸应变层的晶体管,其具有减小的偏移到栅电极的方法及其形成方法
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Application No.: US11566840Application Date: 2006-12-05
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Publication No.: US07659213B2Publication Date: 2010-02-09
- Inventor: Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann
- Applicant: Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries, Inc.
- Current Assignee: GlobalFoundries, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102006019921 20060428
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/42 ; H01L21/8222

Abstract:
By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.
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