Invention Grant
- Patent Title: Method for producing annealed wafer and annealed wafer
- Patent Title (中): 用于生产退火晶片和退火晶片的方法
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Application No.: US11665013Application Date: 2005-10-12
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Publication No.: US07659216B2Publication Date: 2010-02-09
- Inventor: Takatoshi Nagoya
- Applicant: Takatoshi Nagoya
- Applicant Address: JP Tokyo
- Assignee: Shin-Etsu Handotai Co., Ltd.
- Current Assignee: Shin-Etsu Handotai Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Oliff & Berridge, PLC
- Priority: JP2004-299228 20041013
- International Application: PCT/JP2005/018746 WO 20051012
- International Announcement: WO2006/041069 WO 20060420
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
The present invention is a method for producing an annealed wafer, wherein, at least, when a boat in which a semiconductor wafer is placed is inserted into a furnace tube, the boat is inserted along with introducing an inert gas into the furnace, so that entirety of the semiconductor wafer to be a product reaches a thermally uniform portion, then an insertion rate of the boat in which the semiconductor wafer is placed is decelerated and/or suspended, so that an interval between the furnace tube and the shutter is maintained for a predetermined time, and then the furnace tube is blocked in with the shutter. Thereby, there can be provided a method for producing an annealed wafer by which during the heat treatment, it can be more certainly prevented that the wafer is contaminated with conductive impurities and that thereby resistivity of the wafer is changed before and after the heat treatment.
Public/Granted literature
- US20090011613A1 Method for producing annealed wafer and annealed wafer Public/Granted day:2009-01-08
Information query
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