Invention Grant
- Patent Title: Semiconductor device featuring common capacitor electrode layer, and method for manufacturing such semiconductor device
- Patent Title (中): 具有公共电容器电极层的半导体器件及其制造方法
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Application No.: US11656532Application Date: 2007-01-23
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Publication No.: US07659567B2Publication Date: 2010-02-09
- Inventor: Yasuyuki Aoki
- Applicant: Yasuyuki Aoki
- Applicant Address: JP Kawasaki, Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kawasaki, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2006-016770 20060125
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section. A signal-line layer is formed in the insulating layer on or above the conductive structure at the logic-circuit formation section so as to be electrically connected to the conductive structure. An upper-side connection layer are formed in the insulating layer at the memory formation section on or above the capacitors so as to be electrically connected to the upper capacitor electrodes.
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