Invention Grant
US07659569B2 Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region
有权
用于在擦除区域中具有多个电荷存储元件的存储器件的FN擦除的功能工程功能
- Patent Title: Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region
- Patent Title (中): 用于在擦除区域中具有多个电荷存储元件的存储器件的FN擦除的功能工程功能
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Application No.: US11953690Application Date: 2007-12-10
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Publication No.: US07659569B2Publication Date: 2010-02-09
- Inventor: Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Ashot Melik-Martirosian
- Applicant: Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Ashot Melik-Martirosian
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Turocy & Watson, LLP
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L21/336

Abstract:
A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.
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