A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.