The technology of preventing lowering of the element breakdown voltage of a trench gate control type semiconductor element is offered. n− type epitaxial layer (drift region) formed in the main surface side of the substrate, p type semiconductor layer (channel region) formed in n− type epitaxial layer, and p− type well (electric field relaxation layer) which was formed in n− type epitaxial layer in contact with the p type semiconductor layer and whose depth is deeper than the p type semiconductor layer are included. The trench whose depth is deeper than p− type well is patterned in the substrate, and the second gate electrode is formed in the inside of the trench via the insulation film. Among the trenches in the cell area in which power MISFET is formed, one end of p− type well is formed between a plurality of cell trenches in which a second gate electrode is formed, and the other end of p− type well is formed in the peripheral region contiguous to the cell area.