Invention Grant
US07659585B2 ESD protection structure for I/O pad subject to both positive and negative voltages 有权
I / O焊盘的ESD保护结构受到正和负电压的影响

  • Patent Title: ESD protection structure for I/O pad subject to both positive and negative voltages
  • Patent Title (中): I / O焊盘的ESD保护结构受到正和负电压的影响
  • Application No.: US12179243
    Application Date: 2008-07-24
  • Publication No.: US07659585B2
    Publication Date: 2010-02-09
  • Inventor: Gregory Bakker
  • Applicant: Gregory Bakker
  • Applicant Address: US CA Mountain View
  • Assignee: Actel Corporation
  • Current Assignee: Actel Corporation
  • Current Assignee Address: US CA Mountain View
  • Agency: Lewis and Roca LLP
  • Main IPC: H01L23/62
  • IPC: H01L23/62
ESD protection structure for I/O pad subject to both positive and negative voltages
Abstract:
An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to Vcc if it is turned on.
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