Invention Grant
- Patent Title: Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
- Patent Title (中): 使用应变硅锗层的选择性外延的互补金属氧化物半导体晶体管技术
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Application No.: US11746141Application Date: 2007-05-09
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Publication No.: US07659587B2Publication Date: 2010-02-09
- Inventor: Yee-Chia Yeo , Chun-Chieh Lin , Fu-Liang Yang , Chen Ming Hu
- Applicant: Yee-Chia Yeo , Chun-Chieh Lin , Fu-Liang Yang , Chen Ming Hu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.
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