Invention Grant
US07659622B2 Trace design to minimize electromigration damage to solder bumps
有权
跟踪设计,以尽量减少焊料凸块的电迁移损坏
- Patent Title: Trace design to minimize electromigration damage to solder bumps
- Patent Title (中): 跟踪设计,以尽量减少焊料凸块的电迁移损坏
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Application No.: US11779833Application Date: 2007-07-18
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Publication No.: US07659622B2Publication Date: 2010-02-09
- Inventor: Walter J. Dauksher , Dennis H. Eaton
- Applicant: Walter J. Dauksher , Dennis H. Eaton
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/48 ; H01L23/485 ; H01L23/52

Abstract:
A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by dividing current carrying traces into a plurality of sub-traces with known resistances such that each sub-trace distributes a known amount of current to the pad of the integrated circuit. The multiple sub-traces connect to the pad and are placed to obtain a desired uniformity in the incoming current distribution. Width and/or length adjustments could be made to each of the plurality of sub-traces to obtain the desired resistances.
Public/Granted literature
- US20080042271A1 Trace Design to Minimize Electromigration Damage to Solder Bumps Public/Granted day:2008-02-21
Information query
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