Invention Grant
US07659743B2 Method and apparatus for testing electronic components within horizontal and vertical boundary lines of a wafer
失效
用于测试晶片的水平和垂直边界线内的电子部件的方法和装置
- Patent Title: Method and apparatus for testing electronic components within horizontal and vertical boundary lines of a wafer
- Patent Title (中): 用于测试晶片的水平和垂直边界线内的电子部件的方法和装置
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Application No.: US11947206Application Date: 2007-11-29
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Publication No.: US07659743B2Publication Date: 2010-02-09
- Inventor: Stojan Kanev , Jörg Kiesewetter
- Applicant: Stojan Kanev , Jörg Kiesewetter
- Applicant Address: DE Saka
- Assignee: SUSS MicroTec Test Systems GmbH
- Current Assignee: SUSS MicroTec Test Systems GmbH
- Current Assignee Address: DE Saka
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Priority: DE102007005208 20070129
- Main IPC: G01R31/02
- IPC: G01R31/02

Abstract:
A method and an apparatus are provided which make it possible, when testing chips arranged on a wafer, to be able to test optionally both additional components arranged on horizontal boundary lines and on vertical boundary lines. The additional components arranged on horizontal boundary lines are tested in a first position of the wafer. For testing the additional components arranged on vertical boundary lines, the wafer is rotated about its vertical axis through 90° relative to the first position into a second position. The apparatus comprises a housing and, in the housing, at least one test probe for making contact with an electronic component, a chuck for moving the wafer and a rotatably mounted additional plate operatively connected to the chuck.
Public/Granted literature
- US20080180119A1 METHOD FOR TESTING ELECTRONIC COMPONENTS AND TEST APPARATUS FOR CARRYING OUT THE METHOD Public/Granted day:2008-07-31
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