Invention Grant
- Patent Title: Pulsed dynamic logic environment metric measurement circuit
- Patent Title (中): 脉冲动态逻辑环境度量测量电路
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Application No.: US11876100Application Date: 2007-10-22
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Publication No.: US07659749B2Publication Date: 2010-02-09
- Inventor: Kanak B. Agarwal
- Applicant: Kanak B. Agarwal
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Mitch Harris, Atty at Law, LLC; Andrew M. Harris; Libby Z. Handelsman
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage.
Public/Granted literature
- US20090102508A1 Pulsed Dynamic Logic Environment Metric Measurement Circuit Public/Granted day:2009-04-23
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