Invention Grant
- Patent Title: Multiple-output transistor logic circuit
- Patent Title (中): 多输出晶体管逻辑电路
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Application No.: US12005351Application Date: 2007-12-27
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Publication No.: US07659751B2Publication Date: 2010-02-09
- Inventor: Arkadiy Morgenshtein
- Applicant: Arkadiy Morgenshtein
- Applicant Address: IL Haifa
- Assignee: Technion Research & Development Foundation Ltd.
- Current Assignee: Technion Research & Development Foundation Ltd.
- Current Assignee Address: IL Haifa
- Main IPC: H03K19/094
- IPC: H03K19/094 ; H03K19/20

Abstract:
A method of designing logic circuit provides a logic circuit which includes a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. The third transistor network has a complementary structure to the transistors between the intermediate node and the central node, and includes a logic output The third transistor network (the graft network) provides a second logic output to the logic circuit.
Public/Granted literature
- US20080106303A1 Multiple-output transistor logic circuit Public/Granted day:2008-05-08
Information query
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