Invention Grant
- Patent Title: Noise filter circuit
- Patent Title (中): 噪声滤波电路
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Application No.: US11521674Application Date: 2006-09-14
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Publication No.: US07659752B2Publication Date: 2010-02-09
- Inventor: Daisuke Muraoka
- Applicant: Daisuke Muraoka
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2005-273752 20050921
- Main IPC: G01R29/02
- IPC: G01R29/02 ; H03K5/1252

Abstract:
Provided is a noise filter circuit capable of outputting only a normal signal pulse in synchronization with a clock signal without passing the noise pulse on to a subsequent stage, even if a noise pulse having a width that is larger than a delay time is inputted. The noise filter circuit according to the present invention has a flip-flop additionally provided to a stage subsequent to a noise removing circuit that uses a delay circuit. The delay time of a clock signal inputted to the flip-flop is made different from the delay time of the noise removing circuit to thereby obtain a normal signal pulse to be outputted in synchronization with the clock signal.
Public/Granted literature
- US20070066266A1 Noise filter circuit Public/Granted day:2007-03-22
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