Invention Grant
- Patent Title: Conditioning input buffer for clock interpolation
- Patent Title (中): 用于时钟插补的调节输入缓冲器
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Application No.: US12041913Application Date: 2008-03-04
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Publication No.: US07659763B2Publication Date: 2010-02-09
- Inventor: Hibourahima Camara , Sergey V. Rylov
- Applicant: Hibourahima Camara , Sergey V. Rylov
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen J. Walder, Jr.; Diana R. Gerhardt
- Main IPC: H03K3/013
- IPC: H03K3/013

Abstract:
A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.
Public/Granted literature
- US20090224811A1 Conditioning Input Buffer for Clock Interpolation Public/Granted day:2009-09-10
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