A counter circuit increments a count value bit by bit in synchronization with a clock pulse received from an oscillating portion. A lower order decoder receives the count value output from the counter circuit, compares a bit or bits on a lower side with a set value 1, and outputs an H-level only in a time period when the bit or bits match a bit pattern of set value 1. Similarly, an upper order decoder compares a bit or bits on an upper side with a set value 2, and outputs an H-level only in a time period when the bit or bits match the bit pattern of set value 2. An AND circuit renders a transistor conductive in a time period when both lower and upper order decoders are outputting signals of the H-level.