A display control device has: a shift register generating n shift pulses in series; a data hold block configured to hold n gradation data; and a DA converter for converting the n gradation data into corresponding gradation voltages. The data hold block includes: n first latch circuits configured to respectively latch the n gradation data in series in synchronization with the n shift pulses; and n second latch circuits provided between the DA converter and the n first latch circuits. An electrical connection between the first latch circuits and the second latch circuits is cut off while the first latch circuits receive the n gradation data. After the first latch circuits finish latching all the gradation data, the n gradation data are simultaneously supplied to the DA converter from the first latch circuits through the second latch circuits.