Invention Grant
- Patent Title: NAND flash memory
- Patent Title (中): NAND闪存
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Application No.: US11873859Application Date: 2007-10-17
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Publication No.: US07660157B2Publication Date: 2010-02-09
- Inventor: Hiroshi Maejima , Katsuaki Isobe
- Applicant: Hiroshi Maejima , Katsuaki Isobe
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-283457 20061018
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A NAND flash memory, including a memory cell array, a row decoder, and a sense amplifier. In a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by the row decoder, a drain-side select gate line and the source-side select gate line are charged to a third voltage, which is higher than the ground potential and is equal to or lower than the second voltage.
Public/Granted literature
- US20080094903A1 NAND FLASH MEMORY Public/Granted day:2008-04-24
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