Invention Grant
- Patent Title: Integrated flash memory systems and methods for load compensation
- Patent Title (中): 集成闪存系统和负载补偿方法
-
Application No.: US11655901Application Date: 2007-01-19
-
Publication No.: US07660161B2Publication Date: 2010-02-09
- Inventor: Hieu Van Tran
- Applicant: Hieu Van Tran
- Applicant Address: US CA Sunnyvale
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: DLA Piper LLP (US)
- Main IPC: G11C16/06
- IPC: G11C16/06

Abstract:
Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
Public/Granted literature
- US20080175062A1 Integrated flash memory systems and methods for load compensation Public/Granted day:2008-07-24
Information query