A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals.