An integrated circuit 2 with a memory 4 is provided with clock generator circuitry 18. The clock generator circuitry 18 operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal sclk. In a second mode of operation the clock generator circuitry 18 generates the memory clock signal mclk following the rising edge of the source clock signal sclk and then using a self-timing delay path 26 to trigger the falling edge of the memory clock signal mclk. The first mode of operation can be used during write operations and during read operations at the lowest one of a plurality of different dynamically selectable voltage levels of operation of the memory 4. The second mode of self-timed memory clock signal can be used during reads at operating voltages other than the lowest operating voltage.