A focus layer jump control circuit may include a signal processing block that converts an analog focus error (FE) signal into a digital FE signal, in response to the analog FE signal and a FE selection signal; a layer jump control block that outputs a second control signal, in response to the digital FE signal and a reference clock signal; a focus main filter block that outputs first and second compensation signals that amplify the digital FE signal and that compensate for a phase of the digital FE signal, in response to an internal selection signal; an exponent signal generator that generates an exponent signal, in response to a focus layer jump indicating signal and a first control signal; and an output circuit that outputs a first-order difference signal using the exponent signal, the first compensation signal, and the second compensation signal, in response to the second control signal.