Invention Grant
US07660941B2 Two-level RAM lookup table for block and page allocation and wear-leveling in limited-write flash-memories
失效
两级RAM查找表,用于限制写入闪存中的块和页面分配和损耗均衡
- Patent Title: Two-level RAM lookup table for block and page allocation and wear-leveling in limited-write flash-memories
- Patent Title (中): 两级RAM查找表,用于限制写入闪存中的块和页面分配和损耗均衡
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Application No.: US11742270Application Date: 2007-04-30
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Publication No.: US07660941B2Publication Date: 2010-02-09
- Inventor: Charles C. Lee , Frank I-Kang Yu , David Q. Chow
- Applicant: Charles C. Lee , Frank I-Kang Yu , David Q. Chow
- Applicant Address: US CA San Jose
- Assignee: Super Talent Electronics, Inc.
- Current Assignee: Super Talent Electronics, Inc.
- Current Assignee Address: US CA San Jose
- Agency: gPatent LLC
- Agent Stuart T. Auvinen
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.
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