Invention Grant
- Patent Title: Self-synchronizing bit error analyzer and circuit
- Patent Title (中): 自同步位误差分析器和电路
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Application No.: US12154188Application Date: 2008-05-21
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Publication No.: US07661039B2Publication Date: 2010-02-09
- Inventor: Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
- Applicant: Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joseph P. Abate; Daryl K. Neff
- Priority: EP04300840 20040212
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
Public/Granted literature
- US20090019326A1 Self-synchronizing bit error analyzer and circuit Public/Granted day:2009-01-15
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