Invention Grant
US07661040B2 Method of testing a sequential access memory plane and a corresponding sequential access memory semiconductor device
有权
测试顺序存取存储器平面和相应的顺序存取存储器半导体器件的方法
- Patent Title: Method of testing a sequential access memory plane and a corresponding sequential access memory semiconductor device
- Patent Title (中): 测试顺序存取存储器平面和相应的顺序存取存储器半导体器件的方法
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Application No.: US10075113Application Date: 2002-02-13
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Publication No.: US07661040B2Publication Date: 2010-02-09
- Inventor: Marc Beaujoin , Thomas Alofs , Paul Armagnat
- Applicant: Marc Beaujoin , Thomas Alofs , Paul Armagnat
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics S.A.
- Current Assignee: STMicroelectronics S.A.
- Current Assignee Address: FR Montrouge
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Agent Lisa K. Jorgenson
- Priority: FR0102333 20010221
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G01R31/28
Abstract:
The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.
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