Invention Grant
- Patent Title: Test apparatus, and method of manufacturing semiconductor memory
- Patent Title (中): 测试装置和制造半导体存储器的方法
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Application No.: US11477245Application Date: 2006-06-29
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Publication No.: US07661043B2Publication Date: 2010-02-09
- Inventor: Shinya Sato
- Applicant: Shinya Sato
- Applicant Address: JP Tokyo
- Assignee: Advantest Corporation
- Current Assignee: Advantest Corporation
- Current Assignee Address: JP Tokyo
- Agency: Osha•Liang LLP
- Priority: JP2005-194704 20050704
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A test apparatus includes a pattern memory for storing a test pattern to be inputted to a memory-under-test, an address generating section for sequentially outputting addresses of the memory-under-test into which the test pattern is to be written, a pointer section for sequentially pointing each address of the pattern memory to cause the pattern memory to output the test pattern in synchronism with the address of the memory-under-test outputted out of the address generating section, a bad block memory for storing an address of a bad block of the memory-under-test in advance and a pointer control section for causing the address generating section to output a next address of the memory-under-test while holding the address of the pattern memory outputted out of the pointer section when the address of the memory-under-test generated by the address generating section coincides with any one of addresses stored in the bad block memory.
Public/Granted literature
- US20070005286A1 Test apparatus, and method of manufacturing semiconductor memory Public/Granted day:2007-01-04
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