A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode.