Invention Grant
- Patent Title: Multilayer substrate manufacturing method
- Patent Title (中): 多层基板制造方法
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Application No.: US10598469Application Date: 2005-02-24
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Publication No.: US07661191B2Publication Date: 2010-02-16
- Inventor: Takeshi Nakamura , Katsumi Ito
- Applicant: Takeshi Nakamura , Katsumi Ito
- Applicant Address: JP Osaka
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Fish & Richardson P.C.
- Priority: JP2004-059267 20040303
- International Application: PCT/JP2005/003562 WO 20050224
- International Announcement: WO2005/086553 WO 20050915
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
A manufacturing method of a multilayer substrate that suppresses relative displacement of layers and forms interconnecting portions electrically connecting layers having an accurate positioning. A manufacturing method of a multilayer substrate for laminating, via an insulating film, a wiring layer formed by patterning a conductive film comprises providing a positioning hole in a conductive film laminated at the beginning and patterning a second and/or any subsequent wiring layers after identifying a position of an identification section. Interconnecting sections for interconnecting wiring layers are formed using the identification section.
Public/Granted literature
- US20070281459A1 Multilayer Substrate Manufacturing Method Public/Granted day:2007-12-06
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