Invention Grant
US07662665B2 Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging
有权
用于制造包括用于倒装芯片封装的应力消除层的半导体封装的方法
- Patent Title: Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging
- Patent Title (中): 用于制造包括用于倒装芯片封装的应力消除层的半导体封装的方法
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Application No.: US11655844Application Date: 2007-01-22
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Publication No.: US07662665B2Publication Date: 2010-02-16
- Inventor: Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
- Applicant: Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.
Public/Granted literature
- US20080174002A1 Stress relieving layer for flip chip packaging Public/Granted day:2008-07-24
Information query
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