Invention Grant
US07662688B2 Application of different isolation schemes for logic and embedded memory 有权
不同隔离方案在逻辑和嵌入式存储器中的应用

Application of different isolation schemes for logic and embedded memory
Abstract:
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
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