Invention Grant
US07662688B2 Application of different isolation schemes for logic and embedded memory
有权
不同隔离方案在逻辑和嵌入式存储器中的应用
- Patent Title: Application of different isolation schemes for logic and embedded memory
- Patent Title (中): 不同隔离方案在逻辑和嵌入式存储器中的应用
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Application No.: US11848187Application Date: 2007-08-30
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Publication No.: US07662688B2Publication Date: 2010-02-16
- Inventor: Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
- Applicant: Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
Public/Granted literature
- US20080003772A1 Application of Different Isolation Schemes for Logic and Embedded Memory Public/Granted day:2008-01-03
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