Invention Grant
- Patent Title: Integrated process for thin film resistors with silicides
- Patent Title (中): 具有硅化物的薄膜电阻的集成工艺
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Application No.: US11870543Application Date: 2007-10-11
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Publication No.: US07662692B2Publication Date: 2010-02-16
- Inventor: John T. Gasner , John Stanton , Dustin A. Woodbury , James D. Beasom
- Applicant: John T. Gasner , John Stanton , Dustin A. Woodbury , James D. Beasom
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fogg & Powers LLC
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process including, applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and forming interconnect metal layers.
Public/Granted literature
- US20080026536A1 INTEGRATED PROCESS FOR THIN FILM RESISTORS WITH SILICIDES Public/Granted day:2008-01-31
Information query
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