Invention Grant
- Patent Title: Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
- Patent Title (中): 使用薄介电膜形成贯通晶片电互连和其他结构
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Application No.: US12418923Application Date: 2009-04-06
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Publication No.: US07662710B2Publication Date: 2010-02-16
- Inventor: Lior Shiv
- Applicant: Lior Shiv
- Applicant Address: DK Alleroed
- Assignee: Hymite A/S
- Current Assignee: Hymite A/S
- Current Assignee Address: DK Alleroed
- Agency: Fish & Richardson P.C.
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.
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