Invention Grant
- Patent Title: Semiconductor device production method that includes forming a gold interconnection layer
- Patent Title (中): 包括形成金互连层的半导体器件制造方法
-
Application No.: US12005383Application Date: 2007-12-27
-
Publication No.: US07662713B2Publication Date: 2010-02-16
- Inventor: Goro Nakatani , Hitoshi Tamura
- Applicant: Goro Nakatani , Hitoshi Tamura
- Applicant Address: JP Kyoto
- Assignee: Rohm Co., Ltd.
- Current Assignee: Rohm Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Rabin & Berdo, PC
- Priority: JP2003-314240 20030905
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interlevel insulation film; and a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film. The barrier layer is formed in a region of the first interconnection layer including an interlevel connection opening region of the interlevel insulation, and the region is greater than the interlevel connection opening region. The second interconnection layer is electrically connected to the first interconnection layer via the barrier layer in the interlevel connection opening.
Public/Granted literature
- US20080116577A1 Semiconductor device and production method therefor Public/Granted day:2008-05-22
Information query
IPC分类: