Invention Grant
US07663134B2 Memory array with a selector connected to multiple resistive cells
失效
具有选择器的存储器阵列连接到多个电阻单元
- Patent Title: Memory array with a selector connected to multiple resistive cells
- Patent Title (中): 具有选择器的存储器阵列连接到多个电阻单元
-
Application No.: US11775741Application Date: 2007-07-10
-
Publication No.: US07663134B2Publication Date: 2010-02-16
- Inventor: Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
- Applicant: Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L47/00
- IPC: H01L47/00
Abstract:
An array includes a transistor cpmprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
Public/Granted literature
- US20090014836A1 Memory Array with a Selector Connected to Multiple Resistive Cells Public/Granted day:2009-01-15
Information query
IPC分类:
