Invention Grant
US07663193B2 Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region
失效
用于减小存储单元区域的面积的半导体器件及其制造方法
- Patent Title: Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region
- Patent Title (中): 用于减小存储单元区域的面积的半导体器件及其制造方法
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Application No.: US12237693Application Date: 2008-09-25
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Publication No.: US07663193B2Publication Date: 2010-02-16
- Inventor: Nobuo Tsuboi , Motoshige Igarashi
- Applicant: Nobuo Tsuboi , Motoshige Igarashi
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-295258 20051007
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
Public/Granted literature
- US20090026520A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR REDUCING THE AREA OF THE MEMORY CELL REGION Public/Granted day:2009-01-29
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