Invention Grant
US07663204B2 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications
失效
用于多芯片堆叠的基板,利用基板的多芯片堆叠封装及其应用
- Patent Title: Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications
- Patent Title (中): 用于多芯片堆叠的基板,利用基板的多芯片堆叠封装及其应用
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Application No.: US11790826Application Date: 2007-04-27
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Publication No.: US07663204B2Publication Date: 2010-02-16
- Inventor: Hung-Hsin Hsu , Chih-Wei Wu
- Applicant: Hung-Hsin Hsu , Chih-Wei Wu
- Applicant Address: TW Hsinchu
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L23/48

Abstract:
A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes.
Public/Granted literature
- US20080265389A1 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications Public/Granted day:2008-10-30
Information query
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