Invention Grant
- Patent Title: Interposer and stacked chip package
- Patent Title (中): 内插器和堆叠芯片封装
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Application No.: US11446971Application Date: 2006-06-06
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Publication No.: US07663245B2Publication Date: 2010-02-16
- Inventor: Gwang-Man Lim
- Applicant: Gwang-Man Lim
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, PLC
- Priority: KR10-2005-0113375 20051125
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be electrically connected by one end of an electric connection member. Alternatively, each conductive land may provide respective bonding locations to which ends of two different electric connection members may be bonded. A stacked chip package may include an interposer that may be fabricated by cutting an interposer to size. In the stacked chip package, electrical connections may be made through the interposer between an upper semiconductor chip and a package substrate, between the upper semiconductor chip and a lower semiconductor chip, and/or between the lower semiconductor chip and the package substrate.
Public/Granted literature
- US20070120246A1 Interposer and stacked chip package Public/Granted day:2007-05-31
Information query
IPC分类: