Invention Grant
US07663391B2 Test system and method for reducing test signal loss for integrated circuits
有权
用于降低集成电路测试信号损耗的测试系统和方法
- Patent Title: Test system and method for reducing test signal loss for integrated circuits
- Patent Title (中): 用于降低集成电路测试信号损耗的测试系统和方法
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Application No.: US12039742Application Date: 2008-02-29
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Publication No.: US07663391B2Publication Date: 2010-02-16
- Inventor: Shun-Ker Wu
- Applicant: Shun-Ker Wu
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu
- Priority: TW96139498A 20071022
- Main IPC: G01R31/26
- IPC: G01R31/26
Abstract:
An integrated circuit test system includes a probe card, a driver, a receiver, and a first switch. The driver is coupled to the probe card via a first signal line. The receiver is coupled to the probe card via a second signal line. The first switch is coupled between the probe card and the first signal line. After the driver outputs a test signal to a device under test via the first signal line, the first switch is turned off, and then the receiver reads the test signal via the second signal line. Thus, the test signal loss can be reduced.
Public/Granted literature
- US20090102496A1 TEST SYSTEM AND METHOD FOR REDUCING TEST SIGNAL LOSS FOR INTEGRATED CIRCUITS Public/Granted day:2009-04-23
Information query
