Invention Grant
- Patent Title: Synchronous semiconductor device, and inspection system and method for the same
- Patent Title (中): 同步半导体器件及其检测系统及方法相同
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Application No.: US12112782Application Date: 2008-04-30
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Publication No.: US07663392B2Publication Date: 2010-02-16
- Inventor: Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
- Applicant: Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
- Applicant Address: JP Tokyo
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Tokyo
- Agency: Arent Fox LLP
- Priority: JP2000-365053 20001130
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G11C7/00

Abstract:
The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
Public/Granted literature
- US20080204067A1 SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME Public/Granted day:2008-08-28
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