Invention Grant
US07663526B1 Analog-to-digital converter architecture and method with reduced non-linearity 失效
模数转换器架构和方法具有降低的非线性

  • Patent Title: Analog-to-digital converter architecture and method with reduced non-linearity
  • Patent Title (中): 模数转换器架构和方法具有降低的非线性
  • Application No.: US11288930
    Application Date: 2005-11-29
  • Publication No.: US07663526B1
    Publication Date: 2010-02-16
  • Inventor: Ion E. Opris
  • Applicant: Ion E. Opris
  • Main IPC: H03M1/12
  • IPC: H03M1/12
Analog-to-digital converter architecture and method with reduced non-linearity
Abstract:
An analog-to-digital converter circuit and method with reduced non-linearity are described. The circuit includes an amplifier module having at least one active input coupled to at least three capacitor devices. The circuit further includes multiple switches coupled to each respective capacitor device. One switch coupled to each capacitor device is further coupled to an output of the amplifier module, such that each capacitor device can be selectively coupled to the output of the amplifier module. At least one switch coupled to each capacitor device is further coupled to a reference voltage source to receive at least one reference voltage signal. Finally, at least one switch coupled to each capacitor device is further coupled to receive an input voltage signal.
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