Invention Grant
- Patent Title: Tie-off circuit with ESD protection features
- Patent Title (中): 具有ESD保护功能的断电电路
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Application No.: US11137265Application Date: 2005-05-25
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Publication No.: US07663851B2Publication Date: 2010-02-16
- Inventor: Shao-Chang Huang , Jian-Hsing Lee
- Applicant: Shao-Chang Huang , Jian-Hsing Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: K&L Gates LLP
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H3/20 ; H02H9/04 ; H02H3/22

Abstract:
The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.
Public/Granted literature
- US20060268474A1 Tie-off circuit with ESD protection features Public/Granted day:2006-11-30
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