Invention Grant
US07663851B2 Tie-off circuit with ESD protection features 有权
具有ESD保护功能的断电电路

Tie-off circuit with ESD protection features
Abstract:
The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.
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