Invention Grant
- Patent Title: Logic compatible arrays and operations
- Patent Title (中): 逻辑兼容阵列和操作
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Application No.: US11787291Application Date: 2007-04-16
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Publication No.: US07663916B2Publication Date: 2010-02-16
- Inventor: Yue-Der Chih , Te-Hsun Hsu
- Applicant: Yue-Der Chih , Te-Hsun Hsu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.
Public/Granted literature
- US20080251832A1 Logic compatible arrays and operations Public/Granted day:2008-10-16
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