Invention Grant
- Patent Title: Semiconductor memory device having local and global bit lines
- Patent Title (中): 具有局部和全局位线的半导体存储器件
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Application No.: US11946390Application Date: 2007-11-28
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Publication No.: US07663942B2Publication Date: 2010-02-16
- Inventor: Keiichi Kushida
- Applicant: Keiichi Kushida
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-324991 20061130
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A semiconductor memory device includes a plurality of memory cell columns each having a plurality of memory cells, each memory cell including being a static type, a plurality of local bit lines connected to the memory cell columns, a global bit line connected to the local bit lines via a plurality of sense amplifiers, a measurement terminal to which a measurement voltage is applied in a cell current measurement mode, and a plurality of switching circuits provided to correspond to the local bit lines, and configured to electrically connect the measurement terminal and one of the local bit lines in the cell current measurement mode.
Public/Granted literature
- US20080130383A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2008-06-05
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