A semiconductor memory device is capable of stably securing an on-die-termination (ODT) latency in spite of PVT variations and various operating speeds. The semiconductor memory device includes a plurality of termination resistors connected to an output pad in series and parallel, a drive controller, a delay path, and a delay control signal generator. The drive controller activates/inactivates the plurality of termination resistors in response to a driving control signal. The delay path delays a termination command by a delay time corresponding to an on-die-termination (ODT) latency to output the driving control signal, wherein the termination command is converted into a delay locked loop (DLL) clock domain signal. The delay control signal generator controls a conversion point of the termination command into the DLL clock domain signal.